Various embodiments of the present invention are related to systems and methods for evaluating and debugging data decoders, and more particularly to systems and methods for evaluating and debugging low density parity check (LDPC) decoders.
Digital information storage and transmission has become ubiquitous in practically every facet of life throughout most of the world. Various data transfer systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In each of the systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. As information is stored and transmitted in the form of digital data, errors are introduced that, if not corrected, can corrupt the data and render the information unusable. The effectiveness of any transfer is impacted by any losses in data caused by various factors. Many types of error checking systems have been developed to detect and correct errors in digital data. For example, in perhaps the simplest system, a parity bit can be added to a group of data bits, ensuring that the group of data bits (including the parity bit) has either an even or odd number of ones. When using odd parity, as the data is prepared for storage or transmission, the number of data bits in the group that are set to one are counted, and if there is an even number of ones in the group, the parity bit is set to one to ensure that the group has an odd number of ones. If there is an odd number of ones in the group, the parity bit is set to zero to ensure that the group has an odd number of ones. After the data is retrieved from storage or received from transmission, the parity can again be checked, and if the group has an even parity, at least one error has been introduced in the data. At this simplistic level, some errors can be detected but not corrected.
The parity bit may also be used in error correction systems, including in LDPC decoders. An LDPC code is a parity-based code that can be visually represented in a Tanner graph 100 as illustrated in FIG. 1. In an LDPC decoder, multiple parity checks are performed in a number of check nodes 102, 104, 106 and 108 for a group of variable nodes 110, 112, 114, 116, 118, 120, 122, and 124. Variable nodes 110-124 contain values based on a group of data and parity bits that are retrieved from a storage device, received by a transmission system or obtained in some other way. The number and placement of parity bits in the group are selected as the LDPC code is designed. The connections (or edges) between variable nodes 110-124 and check nodes 102-108 are also selected as the LDPC code is designed, balancing the strength of the code against the complexity of the decoder required to execute the LDPC code as data is obtained. The connections between variable nodes 110-124 and check nodes 102-108 may be presented in matrix form as follows, where columns represent variable nodes, rows represent check nodes, and a 1 at the intersection of a variable node column and a check node row indicates a connection between that variable node and check node:
  H  =      [                            1                          0                          0                          1                          0                          1                          1                          0                                      0                          1                          0                          0                          1                          0                          0                          1                                      1                          0                          1                          0                          1                          1                          0                          1                                      0                          1                          0                          1                          0                          0                          1                          1                      ]  
By providing multiple check nodes 102-108 for the group of variable nodes 110-124, redundancy in error checking is provided, enabling errors to be corrected as well as detected. Each check node 102-108 performs a parity check on bits passed as messages from its neighboring (or connected) variable nodes. In the example LDPC code corresponding to the Tanner graph 100 of FIG. 1, check node 102 checks the parity of variable nodes 110, 116, 120 and 122. Values are passed back and forth between connected variable nodes 110-124 and check nodes 102-108 in an iterative process until the LDPC code converges on a value for the group of data and parity bits in the variable nodes 110-124. For example, variable node 110 passes messages to check nodes 102 and 106. Check node 102 passes messages back to variable nodes 110, 116, 120 and 122. The messages between variable nodes 110-124 and check nodes 102-108 are probabilities or beliefs, thus the LDPC decoding algorithm is also referred to as a belief propagation algorithm. Each message from a node represents the probability that a bit has a certain value based on the current value of the node and on previous messages to the node.
A message from a variable node to any particular neighboring check node is computed using any of a number of algorithms based on the current value of the variable node and the last messages to the variable node from neighboring check nodes, except that the last message from that particular check node is omitted from the calculation to prevent positive feedback. Similarly, a message from a check node to any particular neighboring variable node is computed, generally by an XOR function, based on the current value of the check node and the last messages to the check node from neighboring variable nodes, except that the last message from that particular variable node is omitted from the calculation to prevent positive feedback. As iterations are performed in the system, messages pass back and forth between variable nodes 110-124 and check nodes 102-108, with the values in the nodes 102-124 being adjusted based on the messages that are passed, until the values converge and stop changing or until processing is halted.
Because of the iterative nature of the belief propagation algorithm used in LDPC decoders and the changing values in the check nodes 102-108 and variable nodes 110-124, it can be difficult to determine how the LDPC decoder is functioning, how errors might arise, and how the design of the LDPC decoder might be improved or optimized. Further complicating the issue of evaluating and debugging an LDPC decoder, a data detection and decode circuit including an LDPC decoder may utilize two or more global detection and decode iterations to increase the possibility of convergence. Turning to FIG. 2, an exemplary prior art two stage data detection and decode circuit 200 is depicted. Two stage data detection and decode circuit 200 receives a data input 202 that is applied to a detector 206. A hard and soft output from detector 204 is provided to an LDPC decoder 206. Input 202 is fed forward via a buffer 212 to another detector 208. Detector 208 uses a soft output of LDPC decoder 206 and input 202 to perform an additional data detection process. A hard and soft output from detector 208 is provided to an LDPC decoder 210 that performs a second decoding process and provides an output 214. Where the initial detection and decode provided by detector 204 and LDPC decoder 206 does not converge, the subsequent detection and decode provided by detector 208 and LDPC decoder 210 provide an additional opportunity to converge. Such an approach, however, requires two iterations for each input data set introduced as input 202. This may waste significant power and introduce unnecessary latency where the input is capable of converging in a single iteration. Further, in some cases two iterations is insufficient to result in a convergence. Thus, such an approach is both wasteful in some conditions and insufficient in other conditions.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for evaluating and debugging data decoders such as LDPC decoders.